1. Field of the Invention
The present invention relates to a semiconductor device having a circuit structured by a thin film transistor (hereafter referred to as a TFT) on a substrate having an insulating surface, and to a method of manufacture thereof. In particular, the present invention provides an electro-optical device, typically a liquid crystal display device or an EL display device in which a pixel portion and a driver circuit are formed on the same substrate, and provides a technique of suitably utilizing this type of electro-optical device loaded into electronic equipment. Note that, throughout this specification, the term semiconductor device indicates a general device functioning by utilizing semiconductor characteristics, and the above electro-optical device, and equipment in which the electro-optical device is loaded, are included in the category of semiconductor device.
2. Description of the Related Art
A display device structured by a pixel portion in which active elements are arranged is referred to as an active matrix display device, and devices such as a liquid crystal display device and an electroluminescence (hereafter referred to as EL) display device have been developed. An insulating gate type transistor is used in an active element, and a TFT is used ideally. A semiconductor film is formed on a substrate such as glass by a method such as a vapor phase growth method, and, using the semiconductor film, regions such as a channel forming region, a source region, and a drain regions are formed for the TFT. Ideally a material having silicon as its main constituent, such as silicon or silicon germanium, is used in the semiconductor film. Semiconductor films can be classified into amorphous semiconductor films, typically amorphous silicon, and into crystalline semiconductor films, typically polycrystalline silicon, in accordance with their method of manufacture. In addition, techniques for structuring a pixel portion by insulating gate type transistors formed on a single crystal silicon substrate have been developed in recent years.
It is nearly impossible to obtain an electric field effect mobility equal to or greater than 10 cm2/Vsec in a TFT in which an active layer is formed by an amorphous semiconductor (typically amorphous silicon) film due to electrical solid state factors such as the amorphous crystal structure. Therefore, even though they can be used as switching elements for driving a liquid crystal in the pixel portion in an active matrix type liquid crystal display device (switching elements formed by TFTs are hereafter referred to as pixel TFTs), it is impossible to use them to form a driver circuit for performing image display. Consequently, a driver IC is implemented by using a technique such as TAB (tape automated bonding) or COG (chip on glass).
On the other hand, with a TFT having a semiconductor film , typically a crystalline silicon or a polycrystalline silicon, containing a crystalline structure (hereafter referred to as a crystalline semiconductor) as an active layer, a high electric field effect mobility can be obtained, and therefore this type of TFT can form all types of functional circuit and can perform driving. It therefore becomes possible to realize a pixel TFT and, on the same substrate, circuits such as a shift register circuit, a level shifter circuit, a buffer circuit, and a sampling circuit in a driver circuit. The driver circuit is formed by CMOS circuits, composed of n-channel TFTs and p-channel TFTs, as basic units. Techniques of implementing this type of driver circuit are fundamental, and in order to promote making lower weight and thinner liquid crystal display devices, it is thought that a TFT having a crystalline semiconductor layer as an active layer, in which it is possible to form the driver circuit, in addition to the pixel portion, on the same substrate, is suitable.
Forming the active layer by a crystalline semiconductor layer is superior when comparing TFT characteristics, but there are problems in that the manufacturing process becomes complex, and the number of process steps increases, in order to manufacture a TFT corresponding to each circuit in addition to the pixel TFT. It is clear that the increase in the number of process steps is a cause of increased manufacturing costs, and that it leads to a drop in the manufactured yield.
The operating conditions of the pixel TFTs and driver circuit TFTs are not necessarily the same, and therefore the required characteristics of the TFTs also differ greatly. A pixel TFT formed by an n-channel TFT is a switching element which drives a liquid crystal by applying a voltage. The liquid crystal is driven by an AC current therefore a method referred to as frame inversion drive is employed. The pixel TFT is required to have a sufficiently low Off current (the drain current flowing when the TFT is in off operation) in order to maintain an electric charge which has accumulated in a liquid crystal layer for the duration of one frame period. On the other hand, a high driver voltage is applied to the driver circuits, such as a buffer circuit, and therefore a high voltage resistance is required so that the circuit is not damaged due to the high voltage application. Further, in order to increase the electric current driver performance, it is necessary to secure a sufficient value of the On current (the drain current flowing when the TFT is in on operation).
An LDD (lightly doped drain) structure is known as a TFT structure for reducing the value of the Off current. This structure is one in which a region having a low concentration of an added impurity element is formed between a channel forming region and a source region or drain region having a high concentration of an added impurity element, and the low concentration region is referred to as an LDD region. Further, there is a GOLD (gate-drain overlapped LDD) structure, in which the LDD region is arranged so as to overlap a gate electrode through a gate insulating film, as a means of preventing degradation of the On current value due to a hot carrier. It is known that using this type of structure is effective in preventing deterioration phenomena by relieving the high electric field near a drain and protecting against hot carrier injection.
However, the bias state of the pixel TFT and driver circuit TFTs such as those of a shift register circuit and a buffer circuit are not necessarily the same. For example, a large inverse bias is applied to the gate in the pixel TFT (a negative voltage for an n-channel TFT), but driver circuit TFTs basically will not operate in an inverse bias state. Further, the GOLD structure is effective in protecting against degradation of the On current value, but the value of the Off current becomes large by simply overlapping with the gate electrode. On the other hand, although the Off current value control effect is high for a normal LDD structure, it has low effectiveness in relieving the electric field in the vicinity of the drain and therefore in preventing deterioration due to hot carrier injection. This type of problem becomes more tangible, the more the characteristics increase, and the higher the required functionality of the active matrix type liquid crystal display device, particularly in a crystalline silicon TFT. Therefore, considering the different TFT operating state, and considering the prevention of the above hot carrier effect, it is necessary to optimize parameters such as the impurity element concentration of the LDD region, and its distribution.
The present invention is a technique of solving the above problems, and an object of the present invention is to realize an improvement in the operating characteristics and the reliability of a semiconductor device by using appropriate structures, in accordance with circuit function, for TFTs arranged in each circuit of the semiconductor device, typically an active matrix type display device manufactured by using TFTs. In addition, an object of the present invention is to realize a reduction in manufacturing costs, and an increase in yield, by reducing the number of process steps.
In order to realize a reduction in manufacturing costs and an increase in yield, reducing the number of process steps is one means which can be applied. Specifically, it is necessary to reduce the number of photomasks required for TFT manufacture. Photomasks are used in order to form a resist pattern which serves as an etching mask in a photolithography technique, on a substrate. To use one of these photomasks, in addition to steps such as film formation and etching, there are additional steps such as those of resist peeling, cleaning, and drying, and even in the photolithography process, complex steps such as resist application, prebaking, exposure, development, and post baking are performed.
Even while reducing the number of photomasks, the structure of TFTs arranged in each type of circuit is made appropriate in correspondence with the function of the circuit. Specifically, a structure which places emphasis on reducing the value of the Off current more than on operation speed is preferable for a pixel TFT. A multi-gate structure is employed as that type of structure. On the other hand, for a TFT forming a driver circuit in which high speed operation is demanded, it is necessary to use a structure which increases the operation speed and which, at the same time, places emphasis on controlling the conspicuous problem of degradation due to hot carrier injection. This structure is realized by an LDD region of a novel configuration. To be specific, a concentration gradient of an impurity element for controlling conductivity is set in the LDD region formed between a channel forming region and the drain region such that the concentration increases as the distance from the drain region decreases. Thus, an effect can be increased in which the concentration of an electric field in a depletion layer near the drain region is relieved. A portion of the LDD region may also be formed so as to overlap a gate electrode.
In order to form an LDD region having an above-descibed concentration gradient of an impurity element, a method of doping into a semiconductor layer is used, in which an ionized impurity element for controlling conductivity is accelerated by an electric field, and made to pass through a portion of the gate electrode and a gate insulating film (a gate insulating film formed between the gate electrode and the semiconductor layer, and in close contact with both, and an insulating film extending in a region in the periphery of the gate insulating film, is included in the term gate insulating film for the present invention). In addition, the gate electrode is tapered so that the thickness thereof gradually increases from an edge portion of the gate electrode toward the inside, and concentration of the impurity element doped into the semiconductor layer is controlled by utilizing that change in thickness. Namely, the LDD region is formed so that the concentration of the impurity element gradually changes toward the longitudinal direction of the TFT channel.
Specifically, a first etching process is performed for a conductive layer forming the gate electrode, a predetermined region of the conductive layer is removed, and the gate insulating film is exposed in a portion of the region on the semiconductor layer. The conductive layer has a tapered shape at this point in which its thickness gradually increases from the edge portion toward the inside. A first doping process for adding a single conductivity type impurity element is then performed, and the formation of a first low concentration impurity region is performed. Next, a second etching process and a second doping process are similarly performed, and the formation of a second low concentration impurity region is performed. The LDD region is formed from the first and the second low concentration impurity regions. In this case the shape of the gate electrode is determined in accordance with the second etching process, and provided that suitable conditions for the second doping process are selected, a portion of the LDD region can be formed so as to overlap with the gate electrode.
The LDD region is thus formed in the present invention by repeating etching and doping processes a plurality of times. As a result, a plurality of LDD regions in which the concentration with respect to the longitudinal direction of the channel differs, and the impurity element concentration of the LDD region can be changed stepwise or continuously.
It is preferable to use a heat resistant conductive material for the conductive layer forming the gate electrode, and the conductive layer is formed from an element selected from the group consisting of tungsten (W), tantalum (Ta), and titanium (Ti), or from a compound or an alloy having the above elements as constituents. In order to etch this heat resistant conductive material at high speed and with good precision, and in addition, in order to form a tapered shape in the edge portion, it is preferable to apply a dry etching method using a high density plasma. An etching apparatus using microwaves or an inductively coupled plasma (ICP) is suitable as a means for obtaining the high density plasma. In particular, it is easy to control the plasma in an ICP etching apparatus, and it can also respond to a large surface area substrate.
As described above, according to a structure of the present invention, a semiconductor device having a semiconductor layer, an insulating film formed contacting the semiconductor layer, and a gate electrode having a tapered portion on the insulating film, is characterized in that:
the semiconductor layer has: a channel forming region; a first impurity region forming a source region or a drain region containing a single conductivity type impurity element; and a second impurity region forming an LDD region contacting the channel forming region;
a portion of the second impurity region is formed overlapping a gate electrode; and
the concentration of the single conductivity type impurity element contained in the second impurity region increases as distance from the channel forming region increases.
This structure of the present invention can be suitably used in a semiconductor device in which TFTs are formed on a substrate. According to another structure of the present invention, a semiconductor device having an n-channel TFT and a p-channel TFT, is characterized in that:
the semiconductor layer of the n-channel TFT has: a channel forming region; a first impurity region forming a source region or a drain region containing a single conductivity type impurity element; and a second impurity region forming an LDD region contacting the channel forming region;
a portion of the second impurity region is formed overlapping a gate electrode;
the concentration of the single conductivity type impurity element contained in the second impurity region increases as distance from the channel forming region increases;
the semiconductor layer of the p-channel TFT has: a channel forming region; a third impurity region forming a source region or a drain region; and a fourth impurity region forming an LDD region contacting the channel forming region; and
the single conductivity type impurity element and an impurity element, having a conductivity type which is inverse to the conductivity type of the single conductivity type impurity element, are contained in the third impurity region and the fourth impurity region.
A semiconductor device having a pixel portion is characterized in that:
the semiconductor layer of at least one TFT formed in each pixel of the pixel portion has: a channel forming region; a first impurity region forming a source region or a drain region containing a single conductivity type impurity element; and a second impurity region forming an LDD region contacting the channel forming region;
a portion of the second impurity region is formed overlapping a gate electrode; and
the concentration of the single conductivity type impurity element contained in the second impurity region increases as distance from the channel forming region increases.
According to the present invention, a method of manufacturing a semiconductor device of the present invention has:
a first step of forming an insulating film on a semiconductor layer;
a second step of forming a conductive layer on the insulating film;
a third step of selectively etching the conductive layer, forming a conductive layer having a first tapered shape;
a fourth step of doping a single conductivity type impurity element into the semiconductor layer, after completing the third step;
a fifth step of selectively etching the conductive layer having the first tapered shape, forming a conductive layer having a second tapered shape; and
a sixth step of doping a single conductivity type impurity element into the semiconductor layer, after completing the fifth step,
the method being characterized in that the concentration of the single conductivity type impurity element doped in the sixth step is lower than the concentration of the single conductivity type impurity element doped in the fourth step.
This structure of the present invention can be suitably used in a semiconductor device in which TFTs are formed on a substrate. According to another structure of the present invention, a method of manufacturing a semiconductor device having an n-channel thin film transistor and a p-channel thin film transistor, has:
a first step of forming an insulating film on a semiconductor layer of the n-channel thin film transistor and that of the p-channel thin film transistor;
a second step of forming a conductive layer on the insulating film;
a third step of selectively etching the conductive layer, to form a conductive layer having a first tapered shape;
a fourth step of doping a single conductivity type impurity element into the semiconductor layers, after completing the third step;
a fifth step of selectively etching the conductive layer having the first tapered shape, to form a conductive layer having a second tapered shape;
a sixth step of doping a single conductivity type impurity element into the semiconductor layers, after completing the fifth step; and
a seventh step of doping an impurity element, having a conductivity type which is inverse to the conductivity type of the single conductivity type impurity element, into the semiconductor layer of the p-channel thin film transistor, after completing the sixth step,
the method being characterized in that the concentration of the single conductivity type impurity element doped in the sixth step is lower than the concentration of the single conductivity type impurity element doped in the fourth step.
According to still another structure of the present invention, a method of manufacturing a semiconductor device having a pixel portion has:
a first step of forming an insulating film on semiconductor layer that forms a TFT provided in each pixel portions;
a second step of forming a conductive layer on the insulating film;
a third step of selectively etching the conductive layer, forming a conductive layer having a first tapered shape;
a fourth step of doping a single conductivity type impurity element into the semiconductor layer, after completing the third step;
a fifth step of selectively etching the conductive layer having the first tapered shape, forming a conductive layer having a second tapered shape; and
a sixth step of doping a single conductivity type impurity element into the semiconductor layer, after completing the fifth step,
the method being characterized in that the concentration of the single conductivity type impurity element doped in the sixth step is lower than the concentration of the single conductivity type impurity element doped in the fourth step.